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Splitting my time between MPR and RWT

As of January, 2014 I joined the Linley Group as an analyst and senior editor of the Microprocessor Report (MPR), where I am responsible for PC and server processors, and will be lending a hand with...

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AMD’s Jaguar Microarchitecture

Jaguar is AMD’s first 28nm processor, a compact 3.1mm2 design that targets 2-25W devices. It is a derivative of the earlier 40nm Bobcat, a fully out-of-order two issue design, with significant...

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Adaptive Clocking in AMD’s Steamroller

My favorite paper from the ISSCC processor session describes an adaptive clocking technique implemented in AMD’s 28nm Steamroller core that compensates for power supply noise. Initial results show a...

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What’s Next for Moore’s Law? For Intel, III+V = 10nm QWFETs

On the eve of the 50th anniversary of Moore’s Law, the future of silicon CMOS is an open question. With rising costs and uncertain benefits, some semiconductor companies have questioned the wisdom of...

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Tile-based Rasterization in Nvidia GPUs

Starting with the Maxwell GM20x architecture, Nvidia high-performance GPUs have borrowed techniques from low-power mobile graphics architectures. Specifically, Maxwell and Pascal use tile-based...

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A Look Inside Apple’s Custom GPU for the iPhone

Previously, Apple’s iPhones and iPads used PowerVR GPUs from Imagination Technologies for graphics. Based on our analysis, Apple has created a custom GPU that powers the A8, A9, and 10 processors,...

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Intel’s 22FFL Process Improves Power, Cost, and Analog

Intel's 22FFL (FinFET Low-power) is a variant of their existing 22nm process that is aimed at low-cost, extremely low-power, and analog/RF applications. 22FFL relaxes the ground rules to reduce the...

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Intel’s Plans for 3DXP DIMMs Emerge

Intel will offer 3DXP-based DIMMs (previously codenamed Apache Pass) that use the DDR4 interface on the next-generation Cascade Lake server processor. The first DIMMs will be available in 128GB, 256GB,...

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IBM’s Machine Learning Accelerator at VLSI 2018

IBM presented a neural network accelerator at VLSI 2018 showcasing a variety of architectural techniques for machine learning, including a regular 2D array of small processing elements optimized for...

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MRAM Research at VLSI 2018

At VLSI 2018, researchers from TDK and TSMC described advances in Magneto-resistive memory (MRAM). TDK focused on new materials to improve writing for low-voltage MRAM cells at small geometries. A team...

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SuperComputing 19: HPC Meets Machine Learning

For me, SC19 was about the fusion of machine learning and scientific computing. I learned about new technologies from Nvidia, Graphcore, and Cerebras Systems and spoke on a panel about the role of...

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Power Delivery in a Modern Processor

Power delivery is one of the most significant challenges in modern processors. The power delivery network (PDN) must meet the demanding requirements of modern CMOS technology, supply power with...

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Transistor Count: A Flawed Metric

Transistor count and transistor density are often portrayed as technical achievements and milestones. Many vendors brag about the complexity of their design, as measured by transistor count. In...

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Intel 4 Process Scales Logic with Design, Materials, and EUV

The Intel 4 process achieves 20% better performance and scales logic density by 2X while reducing costs through extensive design co-optimization, adoption of new materials, and judicious use of EUV...

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